In order to solve the problem of executing a decision taken by a state machine at the very moment that is required by a particular need, there are two kinds of state machine in the prior art which are commonly used: the Mealy and the Moore state machines.
Those machines are implemented with the required improvements according to the environment and the functions that those state machines are expected to perform. They are used in a synchronous environment, and they do not enable to manage asynchronous events because they take their decisions at moments which depend on their own clock.
The second edition of "Fundamentals of logic design" of Charles H. ROTH, Jr, West Publishing company discloses some fundamental examples of the state machines. The Mealy state machine is represented in FIG. 1. It comprises a combinational circuit (1) which receives a set of input signals (3) and a state variable register (2) whose inputs are generated by the outputs (D1, D2,...,D4) of the combinational circuit. Said state variable register outputs signals (Q1, Q2,...,Q4) which loop back to the combinational circuit. When a set of inputs (X1, X2,..., Xm) is generated to the Mealy state machine, the combinational circuit generates the set of outputs (Z1, Z2,..., Zn) and the flip-flop inputs (D1, D2, .... Dk) which loop back to the combinational logic through the state variable register (2) generating signals (Q1, Q2,..., Q4). This process is repeated for each set of inputs. Instead of using the D flip-flops, a similar model may be used for any type of clocked flip-flop. The clock pulse enables to synchronize the operation of the flip-flops and to prevent the timing problems. The gates in the combinational circuit have finite propagation delays, so when the inputs to the state machine are changed, a finite time is required before the flip-flop inputs reach their final values. Because the gate delays are not all the same, the flip-flop input signals may contain transients and they may change at different times. Since the clock pulse is not applied until all flip-flop input signals have reached their final steady-state values, the unequal gate delays do not cause any timing problems. All flip-flops which must change state do so at the same time. When the flip-flops change state, the new flip-flop outputs are fed back into the combinational circuit. However, no further change in the flip-flop states can occur until the next clock pulse.
The general model for the clocked Moore state machine in FIG. 2 is similar to the clocked Mealy machine. The output decode (9) is separated from the combinational logic (1) and the register (2) in the Moore machine because the outputs set (Z1, Z2,...,Zn) depends only on the present state of the flip-flops and not on the state machine set of inputs (X1, X2 .... , Xm). The operation of the Moore machine is similar to that of the Mealy except when a set of inputs is applied to the Moore machine, the resulting outputs do not appear until after the clock pulse causes the flip-flops to change state.
The main drawback of both state machines is that they cannot be used as such in an asynchronous environment without any improvement, because the moment when the decision is to be taken by the state machine is defined by external asynchronous events independent from the clock of the state machine.
Therefore, in order to solve this problem, one may implement cascading state machines of the Moore type, refer to FIG. 3-A, receiving a set of input signals (X1, X2,...,Xm) on outputs 3-1 and outputting a set of signals (Z1, Z2 .... Zn). The first combinational circuit (1-1) which receives the inputs (X1, X2,...,Xm) comprising the clock select -A/+B input signal (CS) and provides signals (6-1) to its associated latch (2-1) which is driven by signals (7-1) of clock 1 (24 Mz). The latch (2-1) outputs signals (X1-A) to the second combinational circuit (1-2) which also receives inputs (3-2), and signals (X1-B) to the third combinational circuit (1-3) which also receives inputs (3-3), and signals (5-1) which loop back to the combinational circuit (1-1).
The second and third combinational circuits (1-2, 1-3) respectively have their own latches (2-2, 2-3) which are driven by signals (7-2, 7-3) of clocks A and B. Those latches (2-2, 2-3) output signals (51, 52) which loop back to the first combinational circuit (1-1) and signals to the selection circuit (110) of the clock which generates outputs signals (Z1, Z2,...,Zn).
FIGS. 3-B, 3-C and 3-D show the state diagrams of the above cascading state machines used in the prior art. The master state machine (1-1, 2-1) has four states (S1, S2, SOA and SOB) and both slave state machines A and B have the respective states (S3, S4) associated to clock A, (S5, S6) associated to clock B. The state SOA means that clock A is chosen and will be activated at the right moment, so does state of SOB for clock B. It is impossible to have both clocks A and B switched on in the same time, therefore, as long as the CS is at a down-level and clock B is not switched off yet (nonCSononS5), the master state machine remains at SOA state. During that time, the state machines A and B are respectively at state S3 and state S6. As soon as clock B is switched off, the state machine B returns to the state S5, and the master state machine goes to state S1, while the state machine A goes from state S3 to state S4 which means that clock A is switched on. The master state machine is kept in the state S1 as long as the clock select is at a down-level. It goes to state SOB as soon as CS is set at a up-level and it will remain in this state as long as CS is at a down-level and clock A is switched on. During that time state machines A and B are respectively at states S4 and S5.
The passage from SOB to SOA via state S2 is similar to the passage from state SOA to SOB via S1.
The European patent application EP A2 356 940 discloses a finite state machine which enables to take into account a late input. In that finite state machine, the output of a late input is prepared and at the time when the late input is defined an output obtained through a usual process and the output thus prepared are switched in accordance with the late input. This state machine aims to improve the operation speed of the state machine in a synchronous environment where the late input is previously prepared and the output signal is ready to be generated through a selector control circuit to the output register driven a synchronous clock.